Pilot Project Implementation Schedule

The project will be accomplished in three phases.

• First, focused on transfer of technology developed in UCL to ITE.
• Second, focused on development of demonstrator products to be fabricated in small series,
• Third, aimed on extension of the technically matured and commercially justified production to volume producer (e.g. X-FAB, Germany).

First two phases are the subject of this proposal. The third will be undertaken providing that the need for the high volume production will be revealed, however initial agreements (letter of intent) will be prepared beforehand.

Given the two-phase approach mentioned above, the following elements will have to be considered in producing a schedule for the prototype development.

Phase 1

The implementation plan in its first phase consists in a technology transfer of the operating Fully Depleted SOI CMOS technology from UCL towards a CMOS/MEMS unit in Poland to upgrade the existing standard bulk CMOS technology there. The ITE facility is a research & pilot production line organised in a industry-like manner providing contract research ranging from product and technology design, through model and prototype up to small scale, pilot production.  The Fully Depleted SOI CMOS technology is characterized by the use of very thin SOI layers between 30 and  100 nm. The Pilot Project will  thus create a moderate entry cost MEMS/MNT foundry to address industrial applications for Microsystems operating at high temperature, harsh environment  and/or demanding a very stringent power budget.

The technology transfer has been initiated after the Caneus 2004 Conference and resulted in  the following achievements to date:

1-Setting up the UCL – ITE collaboration agreement with the aim of the technology transfer
2-Analysis and discussion of the fully depleted SOI CMOS process. Partitioning and planning of tasks.
3-Transfer of UCL experimental MOSFET characteristics and CMOS design kit. Parameter extraction for EKV MOS model in ITE.
4-Continuation of developments in UCL concerning MEMS compatible and co-integrated with FD SOI CMOS electronics.

To complete the transfer the following activities have to be executed:

1. Agreement on the test structure details and measurement procedures.
2. Fabrication of set of masks for test structure including a simple circuit.
3. At least two (preferably three) full process and device characterization sequence trials in ITE.
4. Device parameter extraction and thus, characterization of the technology, input data for adequate modification of the Technological File
5. Definition of demonstrator specifications (function, temperature range…)
6. Design of the demonstrator device (CMOS circuit part) in two versions:   1st CMOS part only, 2nd CMOS and MEMS.
7. Realization of a preliminary version of the CMOS prototype in UCL according to defined specifications,
8. Transfer and realization of the same CMOS prototype in ITE
9. CMOS-MEMS technology Design and  Integration (UCL – ITE in collaboration)
10. Realization of a preliminary version of the CMOS-MEMS prototype in ITE according to defined specifications,