Powering such complex devices further becomes an ever more important issue, calling for low-power implementations and / or energy scavenging from the environment itself, to reduce the battery problem. Extreme conditions are then to be defined according to the resistance of electronics systems to such constraints, which depends on two aspects : packaging and semiconductor. Semiconductor intrinsic resistance to harsh environment conditions is related to the degradation of the characteristics of transistors with temperature elevation. Most conventional electronics fail above 125-175°C. Out of several contenders (including wide-bandgap materials), only one technology has proved capable to produce the required complex integrated circuits correctly operating at temperatures up to at least 300°C, namely Silicon-on-Insulator or SOI.

Furthermore, SOI also positions as a generic platform for many MEMS and sensors implementation with functionalities and performance of interest for the aerospace applications targeted here : pressure transducers, accelerometers, flame detectors, magnetometers, gas composition and flow sensors, temperature and humidity sensors… Combining or co-integrating several of these developments, i.e. multiple sensors and their read-out CMOS electronics, in a single die or chip, would not only contribute to boost their performance in terms of packing density, data integrity or power consumption, but also to significantly ease their packaging and enhance their reliability, in comparison with traditional hybrid solutions.

Sensor/IC co-integration on SOI substrates has already been validated by low-complexity demonstrators. The recent development of multi-layered SOI substrates which incorporate stacked layers of different semiconductors (silicon, SiC) and dielectrics in various thicknesses renders possible the future vision of three-dimensional co-integration of MEMS, sensors and high-temperature / ultra-low-power CMOS electronics, as proposed here as a pilot project.